本文主要介紹利用FPGA的自身的特性實(shí)現(xiàn)隨機(jī)數(shù)發(fā)生器，在Virtex-II Pro開(kāi)發(fā)板上用ChipScope觀察隨機(jī)數(shù)序列，以及在PCIe4Base（基于Virtex-4 FPGA）上實(shí)現(xiàn)。

基本的原理

隨機(jī)數(shù)在計(jì)算機(jī)科學(xué)中的密碼學(xué)中有著重要的用途，常常被用作密鑰的來(lái)源。隨機(jī)數(shù)包括偽隨機(jī)數(shù)以及真隨機(jī)數(shù)。偽隨機(jī)數(shù)是通過(guò)一定的算法計(jì)算得出，具有類(lèi)似于隨機(jī)數(shù)的統(tǒng)計(jì)特征，這樣的發(fā)生器稱(chēng)為偽隨機(jī)數(shù)發(fā)生器。而真隨機(jī)數(shù)是通過(guò)物理現(xiàn)象產(chǎn)生，例如使用電子元件的噪聲、核裂變等等作為噪聲源[2],這樣的隨機(jī)數(shù)發(fā)生器叫做物理隨機(jī)數(shù)發(fā)生器，也叫做真隨機(jī)數(shù)發(fā)生器（TRNG：Ture Random Number Generator）。

基于FPGA的隨機(jī)數(shù)發(fā)生器基本原理是利用奇數(shù)個(gè)反相器組成振蕩器作為隨機(jī)數(shù)發(fā)生器的噪聲源，因?yàn)橛捎贔PGA自身的特性--信號(hào)傳輸存在抖動(dòng)，所以多個(gè)反相器組成振蕩器輸出也不是很穩(wěn)定的時(shí)鐘信號(hào)，每個(gè)振蕩器輸出不是相同的，這樣成為了理想的噪聲源，見(jiàn)圖1。振蕩器輸出通過(guò)D觸發(fā)器進(jìn)行采樣輸出，采樣頻率是fs，然后多個(gè)采樣輸出結(jié)果經(jīng)過(guò)異或門(mén)之后再通過(guò)一個(gè)D觸發(fā)器進(jìn)行采樣，采樣頻率還是fs。這樣簡(jiǎn)單的隨機(jī)數(shù)發(fā)生器就完成了。

實(shí)現(xiàn)

根據(jù)前面所述的原理圖，進(jìn)行如下設(shè)計(jì)：抽樣頻率是fs為50MHz，用3個(gè)反相器組成一個(gè)振蕩器，共用了25個(gè)振蕩器。因?yàn)檎麄€(gè)結(jié)構(gòu)很簡(jiǎn)單，這里就不多講述，主要想說(shuō)的是振蕩器的描述。為了避免綜合器將振蕩器進(jìn)行一定的優(yōu)化從而背離當(dāng)初的設(shè)計(jì)，所以在代碼中添加了屬性語(yǔ)句，用于保證網(wǎng)絡(luò)不被優(yōu)化掉。見(jiàn)28至31行，36至39行。

1: library IEEE;
2: use IEEE.STD_LOGIC_1164.ALL;
3: use IEEE.STD_LOGIC_ARITH.ALL;
4: use IEEE.STD_LOGIC_UNSIGNED.ALL;
5: ---- Uncomment the following library declaration if instantiating
6: ---- any Xilinx primitives in this code.
7: library UNISIM;
8: use UNISIM.VComponents.all;
9:
10: entity Ring_osc_3 is
11: port ( clk : in STD_LOGIC;
12: D_out : out STD_LOGIC
13: );
14: end Ring_osc_3;
15:
16: architecture Behavioral of Ring_osc_3 is
17: ---------------------------------------
18: -- Interial signal in the Ring_OSC
19: ---------------------------------------
20: signal delay1 : std_logic;
21: signal delay2 : std_logic;
22: signal delay3 : std_logic;
23:
24: ---------------------------------------------------------------------
25: --Attributes to stop delay logic from being optimised.
26: ---------------------------------------------------------------------
27: attribute keep : string;
28: attribute keep of delay1 :signal is "true";
29: attribute keep of delay2 :signal is "true";
30: attribute keep of delay3 :signal is "true";
31:
32: ---------------------------------------------------------------------
33: --Attributes to stop trim logic from being optimised
34: ---------------------------------------------------------------------
35: attribute s : string;
36: attribute s of delay1 : signal is "true";
37: attribute s of delay2 : signal is "true";
38: attribute s of delay3 : signal is "true";
39: 40: ---------------------------------------
41: --Code start
42: ---------------------------------------
43:
44: begin
45: --osc_out is the last invertor output,
46: --and also the output feeds back to the first invertor
47: --invertor 1
48: inv_lut1: LUT1
49: generic map (init => X"1")
50: port map (
51: I0 => delay1,
52: O => delay2);
53:
54: --invertor 2
55: inv_lut2: LUT1
56: generic map (init => X"1")
57: port map (
58: I0 => delay2,
59: O => delay3);
60:
61: --invertor 3
62: inv_lut3: LUT1
63: generic map (init => X"1")
64: port map (
65: I0 => delay3,
66: O => delay1);
67:
68: --D Flip-flop
69: D_ff : FD
70: port map (
71: D => delay3,
72: Q => D_out,
73: C => clk);
74:
75: end Behavioral;
振蕩器最后綜合出來(lái)的結(jié)果是（圖2）：

ChipScope的觀察