Intel公司的MAX 10 FPGA系列采用TSMC 55nm NOR閃存技術,容量從2K到50K 邏輯單元(LE),采用單個或雙核電源電壓和小尺寸3x3mm和高I/O引腳數封裝;器件具有全特性FPGA功能,支持Nios II軟核嵌入處理器,數字信號處理(DSP)區塊以及軟DDR3存儲器控制器,內部存儲雙配置閃存,用戶閃存存儲器,集成了模數轉換器(ADC).主要用在系統管理,I/O擴展,通信控制,工業應用,汽車電子和消費類電子.本文介紹了Intel? MAX? 10 FPGA系列主要優勢,器件平面布局圖以及MAX 10 FPGA開發套件主要特性和電路圖.

Intel? MAX? 10 FPGAs revolutionize non-volatile integration by delivering advanced processing capabilities in a low-cost, single chip small form factor programmable logic device. Building upon the single chip heritage of previous MAX device families, densities range from 2K – 50K LEs, using either single or dual-core voltage supplies. The MAX 10 FPGA family encompasses both advanced small wafer scale packaging (3 mm x 3 mm) and high I/O pin count packages offerings.

MAX 10 FPGAs are built on TSMC’s 55 nm embedded NOR flash technology, enabling instant-on functionality. Integrated features include analog-to-digital converters (ADCs) and dual configuration flash allowing you to store and dynamically switch between two images on a single chip. Unlike CPLDs, MAX 10 FPGAs also include full-featured FPGA capabilities, such as Nios? II soft core embedded processor support, digital signal processing (DSP) blocks, and soft DDR3 memory controllers.

Intel? MAX? 10 devices are single-chip, non-volatile low-cost programmable logic devices (PLDs) to integrate the optimal set of system components.

The highlights of the Intel MAX 10 devices include:
? Internally stored dual configuration flash
? User flash memory
? Instant on support
? Integrated analog-to-digital converters (ADCs)
? Single-chip Nios II soft core processor support
The MAX? 10 devices consist of the following:
? Logic array blocks (LABs)
? Analog-to-digital converter (ADC)
? User flash memory (UFM)
? Embedded multiplier blocks
? Embedded memory blocks (M9K)
? Clocks and phase-locked loops (PLL)
? General purpose I/O
? High-speed LVDS I/O
? External memory interfaces
? Configuration flash memory (CFM)
Intel MAX 10 devices are the ideal solution for system management, I/O expansion,
communication control planes, industrial, automotive, and consumer applications.
Intel? MAX? 10 FPGA系列主要優勢:

圖1. Intel? MAX? 10 FPGA器件平面布局圖

MAX 10 FPGA開發套件

The MAX? 10 FPGA development board provides a hardware platform for evaluating the performanceand features of the Altera? MAX 10 device.
The development kit includes a RoHS- and CE-compliant MAX 10 FPGA Development board with thefollowing components:
? Featured Devices:
? MAX 10 FPGA (10M50D, dual supply, F484 package)
? Enpirion? EN2342QI 4 A PowerSoC Voltage-Mode Synchronous Step-Down Converter withIntegrated Inductor Enpirion
? EN6337QI 3 A High-Efficiency PowerSoC DC-DC Step-Down Converters with Integrated Inductor
? Enpirion EP5358xUI 600 mA PowerSoC DC-DC Step-Down Converters with Integrated Inductor
? MAX II CPLD – EPM1270M256C4N (On-board USB-Blaster? II)
? Programming and Configuration:
? Embedded USB-Blaster II (JTAG)
? Optional JTAG direct via 10-pin header
? Memory Devices:
? 64-Mx16 1 Gb DDR3 SDRAM with soft memory controller
? 128-Mx8 1 Gb DDR3 SDRAM with soft memory controller
? 512-Mb Quad serial peripheral interface (quad SPI) flash
? Communication Ports:
? Two Gigabit Ethernet (GbE) RJ-45 ports
? Ethernet Port A (Bottom)
? Ethernet Port B (Top)
? One mini-USB2.0 UART
? One high-definition multimedia interface (HDMI) video output
? One universal high-speed mezzanine card (HSMC) connector
? Two 12-pin DigilentPmod? compatible connectors
? Analog:
? Two MAX 10 FPGA analog-to-digital converter (ADC) SMA inputs
? 2x10 ADC header
? Potentiometer input to ADC
? One external 16 bit digital-to-analog converter (DAC) device with SMA output
? Clocking
? 25 MHz single-ended, external oscillator clock source
? Silicon labs clock generator with programmable frequency GUI
? Mini-USB cable for on-board USB-Blaster? II
? 2A Power Supply and cord
? Free Quartus? II Web Edition design software (download software and license from website)
? Complete documentation
? User manual, bill of materials, schematic, and board files

圖2. MAX 10 FPGA開發板正面元件圖

圖3. MAX 10 FPGA開發板背面元件圖

圖4. MAX 10 FPGA開發板系統框圖

圖5. MAX 10 FPGA開發板時鐘框圖

圖6. MAX 10 FPGA開發板電路圖(1)

圖7. MAX 10 FPGA開發板電路圖(2)

圖8. MAX 10 FPGA開發板電路圖(3)

圖9. MAX 10 FPGA開發板電路圖(4)

圖10. MAX 10 FPGA開發板電路圖(5)

圖11. MAX 10 FPGA開發板電路圖(6)

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圖13. MAX 10 FPGA開發板電路圖(8)

圖14. MAX 10 FPGA開發板電路圖(9)

圖15. MAX 10 FPGA開發板電路圖(10)

圖16. MAX 10 FPGA開發板電路圖(11)

圖17. MAX 10 FPGA開發板電路圖(12)

圖18. MAX 10 FPGA開發板電路圖(13)

圖19. MAX 10 FPGA開發板電路圖(14)

圖20. MAX 10 FPGA開發板電路圖(15)

圖21. MAX 10 FPGA開發板電路圖(16)

圖22. MAX 10 FPGA開發板電路圖(17)

圖23. MAX 10 FPGA開發板電路圖(18)

圖24. MAX 10 FPGA開發板電路圖(19)

圖25. MAX 10 FPGA開發板電路圖(20)

圖26. MAX 10 FPGA開發板電路圖(21)

圖27. MAX 10 FPGA開發板電路圖(22)

圖28. MAX 10 FPGA開發板電路圖(23)

圖29. MAX 10 FPGA開發板電路圖(24)

圖30. MAX 10 FPGA開發板電路圖(25)

圖31. MAX 10 FPGA開發板電路圖(26)

圖32. MAX 10 FPGA開發板電路圖(27)

圖33. MAX 10 FPGA開發板電路圖(28)

圖34. MAX 10 FPGA開發板電路圖(29)

圖35. MAX 10 FPGA開發板電路圖(30)

圖36. MAX 10 FPGA開發板電路圖(31)