| Function | Memory interface |
| Output frequency (Max) (MHz) | 500 |
| Number of outputs | 26 |
| Output supply voltage (V) | 2.5 |
| Core supply voltage (V) | 2.5 |
| Features | DDR register |
| Operating temperature range (C) | 0 to 70 |
| Rating | Military |
| Output type | SSTL-18 |
| Input type | SSTL-18 |
- Member of the Texas Instruments Widebus? Family
- Operates at 2.3 V to 2.7 V for PC1600, PC2100, and PC2700
- Operates at 2.5 V to 2.7 V for PC3200 (QFN Package)
- Pinout and Functionality Compatible With JEDEC Standard SSTV16859
- 600 ps Faster (Simultaneous Switching) Than the JEDEC Standard SSTV16859 in PC2700 DIMM Applications
- 1-to-2 Outputs to Support Stacked DDR DIMMs
- Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line
- Outputs Meet SSTL_2 Class I Specifications
- Supports SSTL_2 Data Inputs
- Differential Clock (CLK and CLK\) Inputs
- Supports LVCMOS Switching Levels on the RESET\ Input
- RESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
- Pinout Optimizes DIMM PCB Layout
- Latch-Up Performance Exceeds 100mA Per JESD 78, Class II
- ESD Protection Exceeds JESD22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Widebus is a trademark of Texas Instruments.
This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.
All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are edge-controlled LVCMOS circuits optimized for unterminated DIMM loads.
The SN74SSTVF16859 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.
The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up.
