| Sample rate (Max) (MSPS) | 250 |
| Resolution (Bits) | 12 |
| Number of input channels | 2 |
| Interface type | DDR LVDS, Parallel CMOS |
| Analog input BW (MHz) | 700 |
| Features | High Performance |
| Rating | Catalog |
| Input range (Vp-p) | 2 |
| Power consumption (Typ) (mW) | 1250 |
| Architecture | Pipeline |
| SNR (dB) | 70.7 |
| ENOB (Bits) | 11 |
| SFDR (dB) | 98 |
| Operating temperature range (C) | -40 to 85 |
| Input buffer | No |
- Maximum Sample Rate: 250 MSPS
- 14-Bit Resolution – ADS62P49/ADS62P48
- 12-Bit Resolution – ADS62P29/ADS62P28
- Total Power: 1.25 W at 250 MSPS
- Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
- Programmable Gain up to 6dB for SNR/SFDR Trade-Off
- DC Offset Correction
- 90dB Cross-Talk
- Supports Input Clock Amplitude Down to 400 mVPP Differential
- Internal and External Reference Support
- 64-QFN Package (9 mm × 9 mm)
The ADS62Px9/x8 is a family of dual channel 14-bit and 12-bit A/D converters with sampling rates up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 64 QFN package. This makes it well-suited for multi-carrier, wide band-width communications applications.
The ADS62Px9/x8 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available.
It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).
