| Function | Counter |
| Bits (#) | 4 |
| Technology Family | LV-A |
| Supply voltage (Min) (V) | 2 |
| Supply voltage (Max) (V) | 5.5 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Features | Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs, Partial power down (Ioff) |
- Qualified for Automotive Applications
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- 2-V to 5.5-V VCC Operation
- Max tpd of 9.5 ns at 5 V
- Typical VOLP (Output Ground Bounce)
???<0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
???>2.3 V at VCC = 3.3 V, TA = 25°C - Ioff Supports Partial-Power-Down-Mode Operation
- Dual 4-Bit Binary Counters With Individual Clocks
- Direct Clear for Each 4-Bit Counter
- Can Significantly Improve System Densities by Reducing Counter Package Count by 50 Percent
The SN74LV393A contains eight flip-flops and additional gating to implement two individual 4-bit counters in a single package. This device is designed for 2-V to 5.5-V VCC operation.
This device comprises two independent 4-bit binary counters, each having a clear (CLR)\ and a clock (CLK) input. The device changes state on the negative-going transition of the CLK pulse. N-bit binary counters can be implemented with each package, providing the capability of divide by 256. The SN74LV393A has parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system timing signals.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
