高速 CMOS 邏輯雙路 2 位雙穩態透明鎖存器
| Number of channels (#) | 4 |
| Technology Family | HCT |
| Supply voltage (Min) (V) | 4.5 |
| Supply voltage (Max) (V) | 5.5 |
| Input type | TTL-Compatible CMOS |
| Output type | CMOS |
| Clock Frequency (Max) (MHz) | 25 |
| IOL (Max) (mA) | 4 |
| IOH (Max) (mA) | -4 |
| ICC (Max) (uA) | 80 |
| Features | Standard speed (tpd > 50ns), Very high speed (tpd 5-10ns), Partial power down (Ioff) |
- True and Complementary Outputs
- Buffered Inputs and Outputs
- Fanout (Over Temperature Range)
- Standard Outputs...10 LSTTL Loads
- Bus Driver Outputs...15 LSTTL Loads
- Wide Operating Temperature Range . . . –55°C to 125°C
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
- HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il
1μA at VOL, VOH
Data sheet acquired from Harris Semiconductor
The ?HC75 and ?HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected.
