AD9644是一款14位雙通道模數(shù)轉(zhuǎn)換器（ADC），配有一個(gè)高速串行輸出接口，采樣速度可為80MSPS或155MSPS。這款雙通道ADC內(nèi)核采用多級(jí)、差分流水線架構(gòu)，并集成了輸出糾錯(cuò)邏輯。每個(gè)ADC均具有寬帶寬、差分采樣保持模擬輸入放大器，支持用戶可選的各種輸入范圍。集成基準(zhǔn)電壓源可簡(jiǎn)化設(shè)計(jì)。占空比穩(wěn)定器可用來補(bǔ)償ADC時(shí)鐘占空比的波動(dòng)，使轉(zhuǎn)換器保持出色的性能。
　　控制理論
　　The AD9644 dual-core analog-to-digital converter （ADC） can be used for diversity reception of signals， in which the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any fS/2 frequency segment from dc to 250 MHz， using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance.
　　In nondiversity applications， the AD9644 can be used as a base-band or direct downconversion receiver， in which one ADC is used for I input data， and the other is used for Q input data.
　　Synchronization capability is provided to allow synchronized timing between multiple devices. Programming and control of the AD9644 are accomplished using a 3-wire SPI-compatible serial interface.
　　模數(shù)轉(zhuǎn)換器結(jié)構(gòu)
　　The AD9644 architecture consists of a dual front-end sample-and-hold circuit， followed by a pipelined， switched-capacitor ADC. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. Sampling occurs on the rising edge of the clock.
　　Each stage of the pipeline， excluding the last， consists of a low resolution flash ADC connected to a switched-capacitor digital-to-analog converter （DAC） and an interstage residue amplifier （MDAC）。 The MDAC magnifies the difference between the recon-structed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC.
　　The input stage of each channel contains a differential sampling circuit that can be ac- or dc-coupled in differential or single-ended modes. The output staging block aligns the data， corrects errors， and passes the data to the output buffers. The output buffers are powered from a separate supply， allowing digital output noise to be separated from the analog core. During power-down， the output buffers go into a high impedance state.
　　模擬輸入注意事項(xiàng)
　　The analog input to the AD9644 is a differential switched-capacitor circuit that has been designed for optimum performance while processing a differential input signal.
　　The clock signal alternatively switches the input between sample mode and hold mode （see Figure 1）。 When the input is switched into sample mode， the signal source must be capable of charging the sample capacitors and settling within ? of a clock cycle.
　　
　　Figure 1
　　A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore， the precise values are dependent on the application.
　　In intermediate frequency （IF） undersampling applications， any shunt capacitors or series resistors should be reduced since the input sample capacitor is unbuffered. In combination with the driving source impedance， the shunt capacitors limit the input bandwidth. Refer to the AN-742 Application Note， Frequency Domain Response of Switched-Capacitor ADCs; the AN-827 Application Note， A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs; and the Analog Dialogarticle， “Transformer-Coupled Front-End for Wideband A/D Converters，” for more information on this subject （refer to www.analog.com）。
　　For best dynamic performance， the source impedances driving VIN+ and VIN? should be matched， and the inputs should be differentially balanced.
　　輸入模式
　　The analog inputs of the AD9644 are not internally dc biased. In ac-coupled applications， the user must provide this bias externally. Setting the device so that VCM = 0.5 × AVDD （or 0.9 V） is recommended for optimum performance. An on-board common-mode voltage reference is included in the design and is available from the VCMA and VCMB pins. Using the VCMA and VCMB outputs to set the input common mode is recommended. Optimum performance is achieved when the common-mode voltage of the analog input is set by the VCMA and VCMB pin voltages （typically 0.5 × AVDD）。 The VCMA and VCMB pins must be decoupled to ground by a 0.1 μF capacitor. This decoupling capacitor should be placed close to the pin to minimize the series resistance and inductance between the part and this capacitor.