在0.35 μm硅襯底CMOS工藝條件下，分析了集成平面電感器的單片DC/DC變換器的功率損耗，折中考慮了設(shè)計(jì)中的難點(diǎn)以及各種影響因素。優(yōu)化了變換器的轉(zhuǎn)換效率，確定其開(kāi)關(guān)頻率為100 MHz；考慮片上集成平面電感器的單位面積電感值與品質(zhì)因數(shù)的大小也是決定DC/DC變換器性能的關(guān)鍵因素，該文給出了雙層平面螺旋電感器的物理設(shè)計(jì)與幾何參數(shù)優(yōu)化，獲得了雙層平面螺旋電感。模擬結(jié)果表明該變換器工作穩(wěn)定，轉(zhuǎn)換效率可以達(dá)到62%。
關(guān) 鍵 詞 DC/DC變換器; 轉(zhuǎn)換效率; 單片; 平面電感器

Abstract The challenges and tradeoffs in designing a monolithic DC/DC converter including planner inductor using 0.35 μm CMOS technology on silicon substrate are described by analyzing the power dissipation of the converters. The efficiency of the converter is optimized. The physical design and geometric parameters optimization of the desired planar inductor are given. A double-layer spiral inductor with quality factor of 2.3, area of 0.38 square millimeters, inductance of 35 nH are obtained. From the simulated results, a steady Buck converter with the efficiency of 62% is achieved.
Key words DC/DC converter; efficiency; monolithic; planar inductor