在线观看www成人影院-在线观看www日本免费网站-在线观看www视频-在线观看操-欧美18在线-欧美1级

電子發(fā)燒友App

硬聲App

0
  • 聊天消息
  • 系統(tǒng)消息
  • 評(píng)論與回復(fù)
登錄后你可以
  • 下載海量資料
  • 學(xué)習(xí)在線課程
  • 觀看技術(shù)視頻
  • 寫文章/發(fā)帖/加入社區(qū)
會(huì)員中心
創(chuàng)作中心

完善資料讓更多小伙伴認(rèn)識(shí)你,還能領(lǐng)取20積分哦,立即完善>

3天內(nèi)不再提示
創(chuàng)作
電子發(fā)燒友網(wǎng)>電子資料下載>類型>參考設(shè)計(jì)>AD9434本地FMC卡和ML605 Xilinx參考設(shè)計(jì)

AD9434本地FMC卡和ML605 Xilinx參考設(shè)計(jì)

2021-04-23 | pdf | 94.67KB | 次下載 | 3積分

資料介紹

This version (09 Jan 2021 00:45) was approved by Robin Getz.The Previously approved version (19 Mar 2018 17:29) is available.Diff

AD9434 Native FMC Card

Introduction

The AD9434 is a 12-bit monolithic sampling analog-to-digital converter (ADC) optimized for high performance, low power, and ease of use. The part operates at up to a 500 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution. This reference design includes a data capture interface and the external DDR-DRAM interface for sample storage. It allows programming the device and monitoring it's internal status registers. The board also provides other options to drive the clock and analog inputs of the ADC.

Supported Devices

Functional Description

The reference design is built on a Zynq based system parameterized for linux. It consists of three functional modules, a LVDS interface, a PN monitor and a DMA interface. The LVDS interface captures and buffers data from the ADC. The data is captured using ISERDES primitives and is captured 4 samples wide at 1/4th of the ADC clock (125MHz at 500MHz ADC clock). The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software. By default, the board is configured to use the onboard clock.

Supported Carriers

Downloads

Help & Support

13 Feb 2015 18:57 · rejeesh kutty

ML605 Xilinx Reference Design (Obsolete)

Quick Start Guide

The reference design has been tested with ML605. It should be easily portable to other boards such as KC705 and VC707, only the ISERDES primitive, UCF and MHS files need to be changed. The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT). This bit file configuration also captures the test mode outputs of ADC.

Required Hardware

  • ML605 board
  • AD9434-FMC board (the default setup uses onboard clock)
  • Signal generator (for data)

Required Software

  • Xilinx ISE (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). Use the latest version or the one used in the reference design.
  • A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.
  • Xilinx Chipscope Analyzer (for signal capture plot).

Running Demo (SDK) Program

To begin, connect the AD9434-FMC board to the FMC-LPC connector of ML605 board (see image below). Connect power and two USB cables from the PC to the JTAG and UART USB connectors on the edge of the ML605. The demo program uses the default board configuration that uses an on-board clock. Connect a signal source to the AIN SMA (J100) connector of the FMC card. After the hardware setup, turn the power on to the ML605.

Hardware setup

Start IMPACT, and initialize the JTAG chain. The program should recognize the Virtex 6 device. Start a UART terminal (set to 57600 baud rate) and then program the device. If programming was successful, you should be seeing messages appear on the terminal as shown in the figure below. After reading some default registers in the AD9434 and AD9517, the program enables different test patterns available on the ADC.

Terminal

After patterns and prbs sequences are verified, if no errors are present, you may use the chipscope busplot to see the captured signal (see below). The ADC data is available 4-samples wide at 125MHz. The most recent sample is at the most significant bits of the captured data.

Chipscope Busplot

Using the Reference Design

Functional Description

The reference design is built on a microblaze based system parameterized for linux. It consists of three functional modules, a LVDS interface, a PN monitor and a DMA interface. The LVDS interface captures and buffers data from the ADC. The data is captured using ISERDES primitives and is captured 4 samples wide at 1/4th of the ADC clock (125MHz at 500MHz ADC clock). The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.

Registers

Refer to the regmap.txt file inside the pcores directory.

Clock Selection

The board provides different (some modification maybe necessary) possible clock path for clocking the AD9434.

Downloads

FPGA Referece Designs:

Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See generating Xilinx netlist/verilog files from xco files for details.

Tar File Contents

The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to Xilinx EDK documentation for details.

license.txt ADI license & copyright information.
system.mhs MHS file.
system.xmp XMP file (use this file to build the reference design).
data/ UCF file and/or DDR MIG project files.
docs/ Documentation files (Please note that this wiki page is the documentation for the reference design).
sw/ Software (Xilinx SDK) & bit file(s).
../cf_lib/edk/pcores/* The pcores directory.
下載該資料的人也在下載 下載該資料的人還在閱讀
更多 >

評(píng)論

查看更多

下載排行

本周

  1. 1電子電路原理第七版PDF電子教材免費(fèi)下載
  2. 0.00 MB  |  1491次下載  |  免費(fèi)
  3. 2單片機(jī)典型實(shí)例介紹
  4. 18.19 MB  |  95次下載  |  1 積分
  5. 3S7-200PLC編程實(shí)例詳細(xì)資料
  6. 1.17 MB  |  27次下載  |  1 積分
  7. 4筆記本電腦主板的元件識(shí)別和講解說(shuō)明
  8. 4.28 MB  |  18次下載  |  4 積分
  9. 5開關(guān)電源原理及各功能電路詳解
  10. 0.38 MB  |  11次下載  |  免費(fèi)
  11. 6100W短波放大電路圖
  12. 0.05 MB  |  4次下載  |  3 積分
  13. 7基于單片機(jī)和 SG3525的程控開關(guān)電源設(shè)計(jì)
  14. 0.23 MB  |  4次下載  |  免費(fèi)
  15. 8基于AT89C2051/4051單片機(jī)編程器的實(shí)驗(yàn)
  16. 0.11 MB  |  4次下載  |  免費(fèi)

本月

  1. 1OrCAD10.5下載OrCAD10.5中文版軟件
  2. 0.00 MB  |  234313次下載  |  免費(fèi)
  3. 2PADS 9.0 2009最新版 -下載
  4. 0.00 MB  |  66304次下載  |  免費(fèi)
  5. 3protel99下載protel99軟件下載(中文版)
  6. 0.00 MB  |  51209次下載  |  免費(fèi)
  7. 4LabView 8.0 專業(yè)版下載 (3CD完整版)
  8. 0.00 MB  |  51043次下載  |  免費(fèi)
  9. 5555集成電路應(yīng)用800例(新編版)
  10. 0.00 MB  |  33562次下載  |  免費(fèi)
  11. 6接口電路圖大全
  12. 未知  |  30320次下載  |  免費(fèi)
  13. 7Multisim 10下載Multisim 10 中文版
  14. 0.00 MB  |  28588次下載  |  免費(fèi)
  15. 8開關(guān)電源設(shè)計(jì)實(shí)例指南
  16. 未知  |  21539次下載  |  免費(fèi)

總榜

  1. 1matlab軟件下載入口
  2. 未知  |  935053次下載  |  免費(fèi)
  3. 2protel99se軟件下載(可英文版轉(zhuǎn)中文版)
  4. 78.1 MB  |  537793次下載  |  免費(fèi)
  5. 3MATLAB 7.1 下載 (含軟件介紹)
  6. 未知  |  420026次下載  |  免費(fèi)
  7. 4OrCAD10.5下載OrCAD10.5中文版軟件
  8. 0.00 MB  |  234313次下載  |  免費(fèi)
  9. 5Altium DXP2002下載入口
  10. 未知  |  233046次下載  |  免費(fèi)
  11. 6電路仿真軟件multisim 10.0免費(fèi)下載
  12. 340992  |  191183次下載  |  免費(fèi)
  13. 7十天學(xué)會(huì)AVR單片機(jī)與C語(yǔ)言視頻教程 下載
  14. 158M  |  183277次下載  |  免費(fèi)
  15. 8proe5.0野火版下載(中文版免費(fèi)下載)
  16. 未知  |  138039次下載  |  免費(fèi)
主站蜘蛛池模板: 亚洲乱码一区二区三区在线观看 | 免费精品美女久久久久久久久久 | 天天躁夜夜躁狠狠躁躁 | 毛片在线播 | 亚洲 欧美 丝袜 制服 在线 | 高清国产在线 | 精品99久久| 国产特黄一级一片免费 | 色先峰 | 久久亚洲精品国产精品婷婷 | 天天干夜夜玩 | 色女仆影院 | 69日本xxxhd| 欧美一级片网站 | 色综合天天综合网亚洲影院 | 99国产福利 | 亚洲国产精品国产自在在线 | 欧美大香a蕉免费 | 中文字幕在线观看一区二区 | 手机看片久久青草福利盒子 | 欧美特黄一免在线观看 | 在线观看免费视频国产 | 午夜视频在线观看免费视频 | 99久久久久国产精品免费 | 天天做夜夜操 | 婷婷爱五月天 | 成年人午夜影院 | 51影院在线观看成人免费 | 西西人体www303sw大胆高清 | 日本三级免费观看 | 日本人xxxxxxxxx69 | 精品三级视频 | 欧美一级片免费在线观看 | 色小视频| 天天玩天天操 | 日本亚洲欧美国产日韩ay高清 | 日本加勒比在线视频 | 在线精品小视频 | 欧美尺寸又黑又粗又长 | 亚洲国产情侣偷自在线二页 | 人人爱天天做夜夜爽 |