關于晶體諧振器電路應用三個常見誤區

關于晶體諧振器電路應用三個常見誤區，晶科鑫為您整理如下：

Drive level 驅動電平

Applying excessive drive level to the crystal units may cause deterioration of characteristics or damage. Circuit design must be such as to maintain a proper drive level.

若對晶體諧振器施加過大的驅動電平，可能會導致其物理特性惡化或損壞。電路設計必須確保為晶體諧振器提供合適范圍內的驅動電平。針對每一款晶體諧振器Drive level (驅動電平)的大小，晶科鑫的晶體諧振器規格書都有清晰注明。

Negative resistance 負性阻抗

Unless adequate negative resistance is allocated in the oscillation circuit, oscillation start up time may increase or no oscillation may occur. In order to avoid this, provide enough negative resistance in the circuitry design.

在振蕩電路中如果分配的負性阻抗不夠，晶體諧振器振蕩的啟動時間可能會延長或無振蕩頻率產生。請在電路設計時，提供足夠負性阻抗，以確保晶體諧振器正常起振。

Load capacitance 負載電容

Differences in the load capacitance in the oscillation circuit may result in deviations in the oscillation frequency from the desired frequency. Attempting to tune by force may merely cause abnormal oscillation. Before use, please specify the load capacitance of the oscillation circuit.

振蕩電路中負載電容的差異可能導致振蕩頻率與期望頻率產生偏差。若通過強制調諧，可能會導致晶體振蕩器振蕩異常。在晶體諧振器使用之前，請務必確認振蕩電路的負載電容。

審核編輯：湯梓紅