This application note describes the output timing parameters for Altera?
devices, explains how Altera defines tCO results, and presents techniques
for calculating the output timing for your system. In addition, a sample
DDR2 interface link is presented and analyzed for calculating output
timing.
Detailed timing information is available in the device handbooks and
from the Quartus? II software. The timing information in the handbooks
presumes a sample design and is specific to that one implementation for
that device. Your implementation may be different, so you should obtain
timing data that directly applies to your system by using the values
reported by the Quartus II timing analyzer (TAN) or TimeQuest.
When dealing with output timing parameters such as tCO, the Quartus II
software is only aware of the FPGA-related timing components. The
Quartus II software does not have information on the PCB or the
receiving device. It is important to understand exactly what the tCO result
parameters represent and to understand how to use the timing reported
by the Quartus II software to determine complete system timing.