FPGA glossary術(shù)語大全:

A
ACEX An Altera? device family of mid-density, look-up-table (LUT)-based programmable logic devices (PLDs) that offer the low cost and high performance needed for price-sensitive communications applications. See the ACEX 1K Programmable Logic Device Family Data Sheet formore information.
Altera Consultants Alliance Program (ACAP)

An alliance created to provide expert design assistance to users of Altera PLDs. ACAP? consultants provide their expertise and services to designers.
Altera Hardware Description Language (AHDL)

Altera’s design entry language. A high-level modular language that is integrated in the Quartus? II and MAX+PLUS? II development systems.You can create AHDL Text Design Files (.tdf) with the Quartus II and MAX+PLUS II software. AHDL supports Boolean equations,state machines, and conditional and decode logic. AHDL also allows you to create and use parameterized functions and includes full support for functions in the library of parameterized modules (LPM).
Altera Megafunction Partners Program (AMPP)

?An alliance between Altera and the developers of intellectual property cores (megafunctions).The AMPPSM partners bring the advantages of intellectual property cores to users of Altera PLDs.