always @(posedge wr_clk or negedge wr_rst_n) begin
  if (~wr_rst_n) begin
    buff_array  <= {DATA_FIFO_DEPTH{1'b0}};
    vld_array <= {VALID_FIFO_DEPTH{1'b0}};
  end else begin
    if (wr_en) begin
        buff_array[ wr_addr*32  +: 32]  <= wr_data_i;
        vld_array[wr_addr*8 +: 8] <= {8{wr_valid_i}};
      end
    end
  end


reg [10-1:0] rd_valid_bus;
reg [40-1:0]  rd_data_bus;
always @(*) begin
  rd_data_bus[40-1:0]  = buff_array[  rd_addr*40  +: 40];
  rd_valid_bus[10-1:0] = vld_array[rd_addr*10 +: 10];
end
integer i;
reg [40-1:0] rd_data_valid_mask;
always @(*) begin
  for(i = 0; i < 40; i = i + 1) begin
      rd_data_valid_mask[i] = rd_valid_bus[i/4];
  end
end
always @(posedge rd_clk or negedge rd_rst_n) begin
  if (~rd_rst_n) begin
    rd_data_o  <= {40{1'b0}};
    rd_valid_o <= 1'b0;
  end else begin
    if (rd_en) begin
      rd_data_o  <= rd_data_bus & rd_data_valid_mask;
      rd_valid_o <= |rd_valid_bus;
    end else begin
      rd_data_o  <= {40{1'b0}};
      rd_valid_o <= 1'b0;
    end
  end
end