AM1705 Sitara 處理器

描述

AM1705是一款基于ARM926EJ-S的低功耗ARM微處理器。

該設備可用于原始設備制造商（OEM））和原始設計制造商（ODM）通過完全集成的混合處理器解決方案的最大靈活性，快速將具有強大操作系統，豐富用戶界面和高處理器性能的設備推向市場。

ARM926EJ -S是一個32位RISC處理器內核，可執行32位或16位指令并處理32位，16位或8位數據。核心使用流水線操作，以便處理器和內存系統的所有部分可以連續運行。

ARM內核具有協處理器15（CP15），保護模塊以及數據和程序存儲器管理單元（MMU）表后備緩沖區。 ARM內核具有單獨的16KB指令和16 KB數據高速緩存。兩個內存塊都與虛擬索引虛擬標記（VIVT）進行4向關聯。 ARM內核還具有8KB的RAM（向量表）和64KB的ROM。

外設集包括：具有管理數據輸入/輸出（MDIO）模塊的10/100 Mbps以太網MAC（EMAC） ;兩個I ² C總線接口;三個帶有串行器和FIFO緩沖器的多通道音頻串行端口（McASP）;兩個64位通用定時器，每個都可配置（一個可配置為看門狗）;多達8個16引腳的通用輸入/輸出（GPIO），具有可編程中斷/事件生成模式，與其他外設復用;三個UART接口（一個具有 RTS 和 CTS ）;三個增強型高分辨率脈沖寬度調制器（eHRPWM）外設;三個32位增強型捕獲（eCAP）模塊外設，可配置為3個捕獲輸入或3個輔助脈沖寬度調制器（APWM）輸出;兩個32位增強型正交編碼脈沖（eQEP）外設;和2個外部存儲器接口：用于較慢存儲器或外設的異步和SDRAM外部存儲器接口（EMIFA），以及用于SDRAM的高速存儲器接口（EMIFB）。

以太網媒體訪問控制器（EMAC）提供設備和網絡之間的有效接口。 EMAC支持10Base-T和100Base-TX，或半雙工或全雙工模式下的10 Mbps和100 Mbps。此外，MDIO接口可用于PHY配置。

I ² C，SPI和USB2.0端口允許設備輕松控制外圍設備和/或與主機處理器通信。

豐富的外設集提供了控制外部外圍設備和與外部處理器通信的能力。有關每個外設的詳細信息，請參閱本文檔后面的相關章節以及相關的外設參考指南。

該器件具有一整套用于ARM處理器的開發工具。這些工具包括C編譯器和Windows®調試器接口，用于查看源代碼執行情況。

特性

375- and 456-MHz ARM926EJ-S™ RISC Core
- 32-Bit and 16-Bit (Thumb®) Instructions
- Single-Cycle MAC
- ARM Jazelle® Technology
- Embedded ICE-RT™ for Real-Time Debug
ARM9 Memory Architecture
- 16KB of Instruction Cache
- 16KB of Data Cache
- 8KB of RAM (Vector Table)
- 64KB of ROM
Enhanced Direct Memory Access Controller 3 (EDMA3):
- 2 Transfer Controllers
- 32 Independent DMA Channels
- 8 Quick DMA Channels
- Programmable Transfer Burst Size
128KB of RAM Memory
3.3-V LVCMOS I/Os (Except for USB Interface)
Two External Memory Interfaces:
- EMIFA
  - NOR (8-Bit-Wide Data)
  - NAND (8-Bit-Wide Data)
- EMIFB
  - 16-Bit SDRAM With 128-MB Address Space
Three Configurable 16550-Type UART Modules:
- UART0 With Modem Control Signals
- 16-Byte FIFO
- 16x or 13x Oversampling Option
- Autoflow Control Signals (CTS, RTS) on UART0 Only
Two Serial Peripheral Interfaces (SPIs) Each With One Chip Select
Programmable Real-Time Unit Subsystem (PRUSS)
- Two Independent Programmable Real-Time Unit (PRU) Cores
  - 32-Bit Load-Store RISC Architecture
  - 4KB of Instruction RAM per Core
  - 512 Bytes of Data RAM per Core
  - PRUSS can be Disabled Through Software to Save Power
- Standard Power-Management Mechanism
  - Clock Gating
  - Entire Subsystem Under a Single PSC Clock Gating Domain
- Dedicated Interrupt Controller
- Dedicated Switched Central Resource
Multimedia Card (MMC)/Secure Digital (SD) Card Interface With Secure Data I/O (SDIO)
Two Master and Slave Inter-Integrated Circuit (I²C Bus™)
USB 2.0 OTG Port With Integrated PHY (USB0)
- USB 2.0 Full-Speed Client
- USB 2.0 Full- and Low-Speed Host
- End Point 0 (Control)
- End Points 1, 2, 3, and 4 (Control, Bulk, Interrupt, or ISOC) RX and TX
Two Multichannel Audio Serial Ports (McASPs):
- Six Clock Zones and 28 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- FIFO Buffers for Transmit and Receive
10/100 Mbps Ethernet MAC (EMAC):
- IEEE 802.3 Compliant (3.3-V I/O Only)
- RMII Media-Independent Interface
- Management Data I/O (MDIO) Module
One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
Three Enhanced Pulse Width Modulators (eHRPWMs):
- Dedicated 16-Bit Time-Base Counter With Period and Frequency Control
- 6 Single-Edge, 6 Dual-Edge Symmetric, or 3 Dual-Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Chopping by High-Frequency Carrier
- Trip Zone Input
Three 32-Bit Enhanced Capture (eCAP) Modules:
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
- Single-Shot Capture of up to Four Event Timestamps
Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
176-Pin PowerPAD™ Plastic Quad Flat Pack [PTP suffix], 0.5-mm Pin Pitch
Commercial, Industrial, or Extended Temperature