FPGA的有源電容放電電路考慮

　　介紹

　　在電信設備、服務器和數據中心中發現的最新FPGA有多個電源軌，需要對這些系統進行安全的上下排序。高可靠性的DC - DC穩壓器和FPGA電源管理的設計者需要一個簡單的方法來安全地卸下大容量電容器，以避免損壞系統。

　　FPGA Power Sequencing

　　For the latest generation system-on-chip FPGAs， they can have on the order of ten separate power rails supplying the Vcore， memory bus supply， I/O controllers， Ethernet， etc. As shown in Figure 1， each rail is supplied by a DC-DC converter to regulate the required voltage supply of 3.3 V， 2.5 V， 1.8 V， 0.9 V， and more. To power up the system， a particular sequence is followed to ensure safe operation and avoid damaging the system. Likewise during system shutdown， the power sequence is in the reverse order， ensuring each power rail is disabled before the next is switched off. This order is controlled via a Power Sequencer chip that enables each DC-DC regulator as shown in Figure 1.