針對(duì)標(biāo)準(zhǔn)單元模式的超大規(guī)模集成電路布局問題，本文提了一種新的基于線長和時(shí)延雙重優(yōu)化目標(biāo)的布局算法。在以優(yōu)化線長為目標(biāo)函數(shù)的布局結(jié)果基礎(chǔ)上，進(jìn)一步優(yōu)化了芯片的時(shí)延特性，并通過算法設(shè)計(jì)較好地解決了二者優(yōu)化方向的一致性。通過標(biāo)準(zhǔn)單元測試電路的實(shí)驗(yàn)結(jié)果比對(duì)，該算法在線長及時(shí)延優(yōu)化方面綜合性能良好。
關(guān)鍵詞： 互連線；布局；線長；時(shí)延；
A new placement algorithm based on wielength minimization and timing-driven optimization objective WANG Dong-ping, MAO Jun-fa (Dept of Electronic Eng, Shanghai Jiao tong Univ., Shanghai 200030, China) Abstract： Facing the severe challenges of placement in very large scale integrated circuits based on standard cell, a new placement algorithm based on both timing-driven and power minimization optimization objective was presented. Based on the placement result which was optimized by wirelength minimization objective, the delay of the circuit was minimized, besides, this optimization method was well adopted to combine the timing-driven optimization and wirelength minimization. According to the experimental results of MCNC (microelectronics centre of north -Carolina) standard cell benchmarks, the total wielength and longest path delay were both improved.
Key words：interconnect; placement; timing-driven; wirlength