AM3505 Sitara 處理器

數(shù)據(jù)： AM3517, AM3505 Sitara Processors 數(shù)據(jù)表

描述

AM3517 /05是一款高性能ARM Cortex-A8微處理器，速度高達(dá)600 MHz。該器件提供3D圖形加速，同時(shí)還支持眾多外設(shè)，包括DDR2，CAN，EMAC和USB OTG PHY，非常適合工業(yè)應(yīng)用。

該處理器可支持其他應(yīng)用，包括：?jiǎn)伟逵?jì)算機(jī)家庭和工業(yè)自動(dòng)化人機(jī)界面

該設(shè)備支持高級(jí)操作系統(tǒng)（OS），例如：

Linux ^® < /li>
Windows ^® CE
Android™

以下子系統(tǒng)是設(shè)備的一部分：

< ul>

基于ARM Cortex-A8微處理器的微處理器單元（MPU）子系統(tǒng)
PowerVR SGX圖形加速器（僅限AM3517設(shè)備）子系統(tǒng)，用于支持顯示和游戲效果的3D圖形加速
具有多個(gè)功能的顯示子系統(tǒng)，用于多個(gè)并發(fā)圖像處理，以及支持各種顯示的可編程接口。顯示子系統(tǒng)還支持NTSC /PAL視頻輸出。
高性能互連為多個(gè)啟動(dòng)器提供高帶寬數(shù)據(jù)傳輸，用于內(nèi)部和外部存儲(chǔ)器控制器以及片上外設(shè)。該器件還提供全面的時(shí)鐘管理方案。

AM3517 /05器件采用491引腳BGA封裝和484引腳PBGA封裝。

該AM3517 /05數(shù)據(jù)手冊(cè)介紹了AM3517 /05 Sitara處理器的電氣和機(jī)械規(guī)格。

特性

AM3517/05 Sitara Processor:
- MPU Subsystem
  - 600-MHz Sitara ARM Cortex-A8 Core
  - NEON SIMD Coprocessor and Vector
    Floating-Point (FP) Coprocessor
- Memory Interfaces:
  - 166-MHz 16- and 32-Bit mDDR/DDR2
    Interface with 1GB of Total Addressable
    Space
  - Up to 83 MHz General-Purpose Memory
    Interface Supporting 16-Bit-Wide
    Multiplexed Address/DataBus
  - 64KB of SRAM
  - 3 Removable Media Interfaces
    [MMC/SD/SDIO]
- IO Voltage:
  - mDDR/DDR2 IOs: 1.8V
  - Other IOs: 1.8V and 3.3V
- Core Voltage: 1.2V
- Commercial and Extended Temperature Grade
  (operating restrictions apply)
- 16-Bit Video Input Port Capable of
  Capturing HD Video
- HD Resolution Display Subsystem
- Serial Communication
  - High-End CAN Controller
  - 10/100 Mbit Ethernet MAC
  - USB OTG Subsystem with Standard
    DP/DM Interface [HS/FS/LS]
  - Multiport USB Host Subsystem [HS/FS/LS]
    - 12-Pin ULPI or 6-, 4-, or 3-Pin Serial
      Interface
  - Four Master and Slave Multichannel Serial
    Port Interface(McSPI) Ports
  - Five Multichannel Buffered Serial Ports (McBSPs)
    - 512-Byte Transmit and Receive Buffer
      (McBSP1/3/4/5)
    - 5-KB Transmit and Receive Buffer (McBSP2)
    - SIDETONE Core Support (McBSP2 and
      McBSP3 Only)For Filter, Gain, and Mix
      Operations
    - 128-Channel Transmit and Receive Mode
    - Direct Interface to I2S and PCM Device and
      TDM Buses
  - HDQ/1-Wire Interface
  - 4 UARTs (One with Infrared Data Association
    [IrDA] and Consumer Infrared [CIR] Modes)
  - 3 Master and Slave High-Speed Inter-Integrated
    Circuit (I²C) Controllers
  - Twelve 32-bit General-Purpose Timers
  - One 32-bit Watchdog Timer
  - One 32-bit 32-kHz Sync Timer
  - Up to 186 General-Purpose I/O (GPIO) Pins
Display Subsystem
- Parallel Digital Output
- Up to 24-Bit RGB
- Supports Up to 2 LCD Panels
- Support for Remote Frame Buffer Interface (RFBI)
  LCD Panels
- Two 10-Bit Digital-to-Analog Converters (DACs)
  Supporting
  - Composite NTSC/PAL Video
  - Luma/Chroma Separate Video (S-Video)
- Rotation of 90, 180, and 270 Degrees
- Resize Images From 1/4x to 8x
- Color Space Converter
- 8-Bit Alpha Blending
Video Processing Front End (VPFE) 16-Bit Video Input Port
- RAW Data Interface
- 75-MHz Maximum Pixel Clock
- Supports REC656/CCIR656 Standard
- Supports YCbCr422 Format (8-Bit or 16-Bit with Discrete
  Horizontal and Vertical Sync Signals)
- Generates Optical Black Clamping Signals
- Built-in Digital Clamping and Black Level Compensation
- 10-Bit to 8-Bit A-law Compression Hardware
- Supports up to 16K Pixels (Image Size) in Horizontal
  and Vertical Directions
System Direct Memory Access (sDMA) Controller (32 Logical
Channels with Configurable Priority)
Comprehensive Power, Reset, and Clock Management
ARM Cortex-A8 Memory Architecture
- ARMv7 Architecture
- In-Order, Dual-Issue, Superscalar Microprocessor Core
- ARM NEON Multimedia Architecture
- Over 2x Performance of ARMv6 SIMD
- Supports Both Integer and Floating-Point SIMD
- Jazelle RCT Execution Environment Architecture
- Dynamic Branch Prediction with Branch Target Address
  Cache, Global History Buffer and 8-Entry Return Stack
- Embedded Trace Macrocell [ETM] Support for
  Noninvasive Debug
- 16KB of Instruction Cache (4-Way Set-Associative)
- 16KB of Data Cache (4-Way Set-Associative)
- 256KB of L2 Cache
PowerVR SGX Graphics Accelerator (AM3517 Only)
- Tile-Based Architecture Delivering up to 10 MPoly/sec
- Universal Scalable Shader Engine: Multi-threaded Engine
  Incorporating Pixel and Vertex Shader Functionality
- Industry Standard API Support: OpenGLES 1.1 and
  2.0, OpenVG1.0
- Fine-Grained Task Switching, Load Balancing, and
  Power Management
- Programmable, High-Quality Image Anti-Aliasing
Endianess
- ARM Instructions – Little Endian
- ARM Data – Configurable
SDRC Memory Controller
- 16- and 32-Bit Memory Controller with 1GB of
  Total Address Space
- Double Data Rate (DDR2) SDRAM, Mobile Double Data Rate
  (mDDR)SDRAM
- SDRAM Memory Scheduler (SMS) and Rotation Engine
General Purpose Memory Controller (GPMC)
- 16-Bit-Wide Multiplexed Address/Data Bus
- Up to 8 Chip-Select Pins with 128MB of Address
  Space per Chip-Select Pin
- Glueless Interface to NOR Flash, NAND Flash (with ECC
  Hamming Code Calculation), SRAM and Pseudo-SRAM
- Flexible Asynchronous Protocol Control for Interface
  to Custom Logic (FPGA, CPLD, ASICs, and so forth)
- Nonmultiplexed Address/Data Mode (Limited 2-KB
  Address Space)
Test Interfaces
- IEEE-1149.1 (JTAG) Boundary-Scan Compatible
- Embedded Trace Macro Interface (ETM)
65-nm CMOS Technology
Packages:
- 491-Pin BGA (17 x 17, 0.65-mm Pitch)
  [ZCN Suffix]
  with Via Channel Array
  Technology
- 484-Pin PBGA (23 x 23, 1-mm Pitch)
  [ZER Suffix]

參數(shù) 與其它產(chǎn)品相比 AM3x


Arm MHz (Max.)
Serial I/O
Graphics Acceleration
EMAC
DRAM
Operating Temperature Range (C)
Approx. Price (US$)

AM3505	AM3517
600	600
USB I2C McBSP McSPI UART CAN	USB I2C McBSP McSPI UART CAN
	1 3D
10/100	10/100
DDR2 LPDDR	DDR2 LPDDR
-40 to 105 0 to 90	-40 to 105 0 to 90
15.94 \| 1ku	18.37 \| 1ku