AM3892 Sitara 處理器

數據： AM389x Sitara ARM Microprocessors (MPUs) 數據表

描述

AM389x Sitara ARM處理器是一個高度集成的可編程平臺，利用TI的Sitara技術來滿足以下應用的處理需求：單板計算，網絡和通信處理，工業自動化，人機界面和交互式服務點信息亭。

該設備使原始設備制造商（OEM）和原始設計制造商（ODM）能夠快速實現市場設備具有強大的操作系統支持，豐富的用戶界面和高處理性能，通過完全集成的混合處理器解決方案的最大靈活性。該器件將高性能ARM 處理與高度集成的外設集合在一起。

具有NEON浮點擴展的ARM Cortex-A8 32位RISC處理器包括：32KB指令緩存; 32KB的數據緩存; 256KB的L2緩存;和64KB的RAM。

豐富的外設集可以控制外部外圍設備并與外部處理器通信。有關每個外圍設備的詳細信息，請參閱本文檔中的相關章節以及相關的外圍設備參考指南。外圍設備包括：高清視頻處理子系統（HDVPSS），提供同步高清和標清模擬視頻輸出和雙高清視頻輸入;最多兩個千兆以太網MAC（10 Mbps，100 Mbps，1000 Mbps），帶有GMII和MDIO接口;兩個USB端口，集成2.0 PHY; PCIe端口x2通道符合GEN2標準接口，允許設備充當PCIe根復合體或設備端點;一個6聲道McASP音頻串口（帶DIT模式）;兩個雙通道McASP音頻串口（帶DIT模式）;一個McBSP多通道緩沖串口;三個支持IrDA和CIR的UART; SPI串行接口; SD和SDIO串行接口;兩個I ² C主從接口;最多64個GPIO引腳;七個32位定時器;系統看門狗定時器;雙DDR2和DDR3 SDRAM接口;靈活的8位和16位異步存儲器接口;最多兩個SATA接口，可通過端口倍增器在兩個或更多磁盤驅動器上進行外部存儲。

該設備還包括一個SGX530 3D圖形引擎（僅在AM3894設備上可用），以關閉從核心加載許多視頻和圖像處理任務。此外，該設備還有一套完整的ARM開發工具，包括C編譯器和Microsoft Windows調試器界面，可以查看源代碼執行情況。

設備包已經采用Via Channel技術專門設計。該技術允許在這種0.65 mm間距封裝中使用0.8 mm間距PCB特征尺寸，從而大幅降低PCB成本。由于Via Channel BGA技術的層效率提高，Via Channel技術還允許僅在兩個信號層中進行PCB布線。

特性

High-Performance Sitara ARM Microprocessors (MPUs)
- ARMCortex-A8 RISC Processor
  - Up to 1.20 GHz
ARM Cortex-A8 Core
- ARMv7 Architecture
  - In-Order, Dual-Issue, Superscalar Processor Core
  - NEON Multimedia Architecture
- Supports Integer and Floating Point (VFPv3-IEEE754 Compliant)
  - Jazelle RCT Execution Environment
ARM Cortex-A8 Memory Architecture
- 32-KB Instruction and Data Caches
- 256-KB L2 Cache
- 64-KB RAM, 48-KB of Boot ROM
512KB of On-Chip Memory Controller (OCMC) RAM
SGX530 3D Graphics Engine (Available Only on the AM3894 Device)
- Delivers up to 30 MTriangles per Second
- Universal Scalable Shader Engine
- Direct3D Mobile, OpenGL ES 1.1 and 2.0, OpenVG 1.1, OpenMax API Support
- Advanced Geometry DMA Driven Operation
- Programmable HQ Image Anti-Aliasing
Endianness
- ARM Instructions and Data – Little Endian
HD Video Processing Subsystem (HDVPSS)
- Two 165-MHz HD Video Capture Channels
  - One 16-Bit or 24-Bit and One 16-Bit Channel
  - Each Channel Splittable Into Dual 8-Bit Capture Channels
- Two 165-MHz HD Video Display Channels
  - One 16-Bit, 24-Bit, 30-Bit Channel and One 16-Bit Channel
- Simultaneous SD and HD Analog Output
- Digital HDMI 1.3 Transmitter with PHY with HDCP up to 165-MHz Pixel Clock
- Three Graphics Layers
Dual 32-Bit DDR2 and DDR3 SDRAM Interfaces
- Supports up to DDR2-800 and DDR3-1600
- Up to Eight x8 Devices Total
- 2GB of Total Address Space
- Dynamic Memory Manager (DMM)
  - Programmable Multi-Zone Memory Mapping and Interleaving
  - Enables Efficient 2D Block Accesses
  - Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
  - Optimizes Interlaced Accesses
One PCI Express (PCIe) 2.0 Port with Integrated PHY
- Single Port with 1 or 2 Lanes at 5.0 GT per Second
- Configurable as Root Complex or Endpoint
Serial ATA (SATA) 3.0 Gbps Controller with Integrated PHYs
- Direct Interface for Two Hard Disk Drives
- Hardware-Assisted Native Command Queuing (NCQ) from up to 32 Entries
- Supports Port Multiplier and Command-Based Switching
Two 10 Mbps, 100 Mbps, and 1000 Mbps Ethernet MACs (EMAC)
- IEEE 802.3 Compliant (3.3-V I/O Only)
- MII and GMII Media Independent Interfaces
- Management Data I/O (MDIO) Module
Dual USB 2.0 Ports with Integrated PHYs
- USB 2.0 High-Speed and Full-Speed Client
- USB 2.0 High-Speed, Full-Speed, and Low-Speed Host
- Supports Endpoints 0-15
General-Purpose Memory Controller (GPMC)
- 8-Bit and 16-Bit Multiplexed Address and Data Bus
- Up to 6 Chip Selects with up to 256-MB Address Space per Chip Select Pin
- Glueless Interface to NOR Flash, NAND Flash (with BCH and Hamming Error Code Detection), SRAM and Pseudo-SRAM
- Error Locator Module (ELM) Outside of GPMC to Provide up to 16-Bit and 512-Byte Hardware ECC for NAND
- Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs
Enhanced Direct-Memory-Access (EDMA) Controller
- Four Transfer Controllers
- 64 Independent DMA Channels and 8 Quick DMA (QDMA) Channels
Seven 32-Bit General-Purpose Timers
One System Watchdog Timer
Three Configurable UART, IrDA, and CIR Modules
- UART0 with Modem Control Signals
- Supports up to 3.6864 Mbps UART
- SIR, MIR, FIR (4.0 MBAUD), and CIR
One 40-MHz Serial Peripheral Interface (SPI) with Four Chip Selects
SD and SDIO Serial Interface (1-Bit and 4-Bit)
Dual Inter-Integrated Circuit (I²C bus) Ports
Three Multichannel Audio Serial Ports (McASPs)
- One Six-Serializer Transmit and Receive Port
- Two Dual-Serializer Transmit and Receive Ports
- DIT-Capable For SDIF and PDIF (All Ports)
Multichannel Buffered Serial Port (McBSP)
- Transmit and Receive Clocks up to 48 MHz
- Two Clock Zones and Two Serial Data Pins
- Supports TDM, I2S, and Similar Formats
Real-Time Clock (RTC)
- One-Time or Periodic Interrupt Generation
Up to 64 General-Purpose I/O (GPIO) Pins
On-Chip ARM ROM Bootloader (RBL)
Power, Reset, and Clock Management
- SmartReflex Technology (Level 2)
- Seven Independent Core Power Domains
- Clock Enable and Disable Control For Subsystems and Peripherals
IEEE 1149.1 (JTAG) and IEEE 1149.7 (cJTAG) Compatible
Via Channel Technology Enables use of
0.8-mm Design Rules
40-nm CMOS Technology
3.3-V Single-Ended LVCMOS I/Os (Except for DDR3 at 1.5 V, DDR2 at 1.8 V, and DEV_CLKIN at 1.8 V)

參數與其它產品相比 AM3x


Arm MHz (Max.)
Serial I/O
Graphics Acceleration
EMAC
DRAM
Operating Temperature Range (C)
Approx. Price (US$)

AM3892	AM3894
1200	1200
USB I2C McASP McBSP McSPI UART SATA	USB I2C McASP McBSP McSPI UART SATA
	1 3D
10/100/1000	10/100/1000
DDR2 DDR3	DDR2 DDR3
0 to 95	-40 to 105 0 to 95
48.58 \| 1ku	50.99 \| 1ku
無樣片	無樣片